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 ML12509 ML12511 ML12513
MECL PLL Components Dual Modulus Prescaler
Legacy Device: Motorola 12509, 12511, 12513
These devices are two-modulus prescalers which will divide by 5 and 6, 8 and 9, respectively. A MECL-to-MTTL translator is provided to interface directly with the Motorola MC12014 Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source. * ML12509 480 MHz (/5/6), ML12511 550 MHz (/8/9), ML12513 550 MHz (/10/11) * MECL to MTTL Translator on Chip * MECL and MTTL Enable Inputs * 5.0 or -5.2 V Operation* * Buffered Clock Input -- Series Input RC Typ, 20 and 4.0 pF * VBB Reference Voltage * 310 mW (Typ) * When using a 5.0 V supply, apply 5.0 V to Pin 1 (VCCO), Pin 6 (MTTL VCC), Pin 16 (VCC), and ground Pin 8 (VEE). When using -5.2 V supply, ground Pin 1 (VCCO), Pin 6 (MTTL VCC), and Pin 16 (VCC) and apply -5.2 V to Pin 8 (VEE). If the translator is not required, Pin 6 may be left open to conserve DC power drain.
16 1
CERDIP 16 = E CERAMIC PACKAGE CASE 620 CROSS REFERENCE/ORDERING INFORMATION PACKAGE MOTOROLA LANSDALE CERDIP 16 CERDIP 16 CERDIP 16 12509/BEA 12511/BEA 12513/BEA ML12509/BEA ML12511/BEA ML12513/BEA
PIN CONNECTIONS
VCCO Q Q (-) (+) MTTL VCC MTTL Output VEE
1 2 3 4 5 6 7 8 (Top View)
16 VCC 15 Clock 14 VBB 13 E1 MECL 12 E2 MECL 11 E3 MECL 10 E4 MECL 9 E5 MECL
MAXIMUM RATINGS
Characteristic Symbol Rating Unit
(Ratings above which device life may be impaired) Power Supply Voltage (VCC = 0) Input Voltage (VCC = 0) Output Source Current Continuous Surge Storage Temperature Range VEE Vin IO 50 100 Tstg -65 to 175 C -8.0 0 to VEE Vdc Vdc mAdc
(Recommended Maximum Ratings above which performance may be degraded) Operating Temperature Range DC Fan-Out (Note 1) (Gates and Flip-Flops) TA n -55 to 125 70 C --
NOTES: 1. AC fan-out is limited by desired system performance.
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ML12509, ML12511, ML12513
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ELECTRICAL CHARACTERISTICS
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ELECTRICAL CHARACTERISTICS
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SWITCHING CHARACTERISTICS
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LANSDALE Semiconductor, Inc.
Figure 5. AC Test Circuit
Vin VCC = 2.0 V Vout (Scope Channel B)
50 Pulse Generator #1 100
25 F
1
6
16
0.1 F
Vout
Vin
13 12
E1 E2 E3 E4 E5 C Q
2
Pulse Generator #2
50 100 Vin
11 10 9 15
3 Q
Vout
14 950 Pulse Generator #3 5 50 +
VBB 1950 7
4
-
MECL to MTTL Trans- lator 8
Pulse Generator #4
Vin (Scope Channel A) MC10109 or equiv. A
0.1 F VEE = -3.0 V
CT
All Pulse Generators are EH 137 or equiv. Pulse Generators 1, 2 and 4: PRF = 10 MHz PW = 50% Duty Cycle t + = t - = 2.0 0.2 ns Pulse Generator 3: PRF = 2.0 MHz PW = 50% Duty Cycle t + = t - = 5.0 0.5 ns
50 VEE = -3.0 V
All resistors are +1%. All input and output cables to the scope are equal lengths of 50 coaxial cable. The 1950 resistor at Pin 7 and the scope termination impedance constitute a 40 :1 attenuator probe. CT = 15 pF = total parasitic capacitance which includes probe, wiring, and load capacitance. Unused output connected to a 50 resistor to ground.
NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and ground voltages must be maintained between tests. The clock input is the waveform shown. 2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock input is the waveform shown. 3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock input is the waveform shown.
Clock Input VIHmax VILmin
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50 resistor to -2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same manner.
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ML12509, ML12511, ML12513
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Figure 3. AC Voltage Waveforms
Pulse Generator 4 and 1 t++ Q (Pin 2) 50% 80% 50% 20% VIHmin VILmin
t+ -
Q (Pin 3) 50%
+ In MTTL Out
50% t++ t--
-1.5 V
Figure 4. Setup and Release Time Waveforms
Pulse 50 Generator % 1 tsetup1 Pulse Generator tsetup2 2 Pulse Generator +1.5 V 3 Q (Pin 2) 80% 20% 80% 50% 90% 10% Divide by 5 -- ML12509 Divide by 8 -- ML12511 Divide by 10 -- ML12513 20% VIHmin VILmin VIHmin VILmin 0V VEE Pulse Generator 1 Pulse 50% Generator t rel2 2 Pulse Generator 3 -1.5 V Q (Pin 2) 80% 20% VIHmin VILmin VIHmin VILmin 0V VEE
50% trel1 80% 20% 90% 10%
Divide by 6 -- ML12509 Divide by 9 -- ML12511 Divide by 11 -- ML12513
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LANSDALE Semiconductor, Inc.
Figure 6. Maximum Frequency Test Circuit
VCC = 2.0 V 0.1 F 5.0 F Vout to Scope
1
16
13 E1 Vin (To Scope) VEE 11 E3 10 9 0.1 F 15 C 1.0 k 14 VBB 0.1 F 8 0.1 F VEE = -3.0 V
Unused output connected to a 50 resistor to ground
12 E2
Q
2
E4 E5 Q 3
800 mV Clock Input
DIVIDE BY 6
850 mV typ Q (Pin 2) 3 Cycles 3 Cycles
DIVIDE BY 9 800 mV Clock Input 850 mV typ Q (Pin 2) 5 Cycles 4 Cycles
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ML12509, ML12511, ML12513
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LANSDALE Semiconductor, Inc.
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ML12509, ML12511, ML12513 OUTLINE DIMENSIONS
CERDIP 16 = E CERAMIC PACKAGE (ML12509/BEA, ML12511/BEA, ML12513/BEA) CASE 620
LANSDALE Semiconductor, Inc.
Lansdale Semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Lansdale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. "Typical" parameters which may be provided in Lansdale data sheets and/or specifications can vary in different applications, and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts. Lansdale Semiconductor is a registered trademark of Lansdale Semiconductor, Inc.
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